The present invention relates to a multi-rate clock generator for generating clocks in accordance with a plurality of channel data rates from reproduction data gained by A/D conversion of reproduction signals and a multi-rate digital data reproducing device for reproducing recorded digital signals at a plurality of channel rates.
In recent years a system of reproduction by varying the number of reproduction channels and cylinder revolutions has been used quite often for the reproduction of recording tapes with different formats in a reproduction unit for digitally recorded magnetic tape.
For example, as a tape format for broadcasting tasks which digitally record video signals, there are DVCPRO and DVCPRO50, which is the high picture quality versions of DVCPRO. Those formats have exactly the same recording wave length on the tape, track pitch, track angle on the tape and number of cylinder revolutions. Total recording data rate per unit hour, however, is twice as high in DVCPRO50 as in DVCPRO.
Therefore, recording and reproducing are carried out with one channel (two heads) at 41.85 Mbps/ch in DVCPRO while recording and reproducing are carried out with two channels (four heads) at 41.715 Mbps/ch in DVCPRO50. Accordingly, data of one frame of picture signals are recorded as 10 tracks in DVCPRO while recorded as 20 tracks in DVCPRO50.
Since formats for recording tapes DVCPRO50 and recording tapes DVCPRO are different in general, video tape recorders corresponding to them, respectively, are necessary for reproducing both of them.
In addition, it is understood that since the tape format of DVCPRO50 is the same as that of DVCPRO in the track angle on the tape, the head is on track on the track of the tape of DVCPRO by cutting the tape speed in half and the revolutions in half in the video tape recorder of DVCPRO50.
Therefore, by cutting the number of cylinder revolutions and the tape speed of the video tape recorder of DVCPRO50 in half and by reproducing with two channels (four heads) at 20.8575 Mbps/ch, the DVCPRO tape can be reproduced in a convertible manner. At this time since the reproduction channel data rate is 20.8575 Mbps which is one half of 41.715 Mbps, DVCPRO50 needs a clock reproduction circuit and reproduction equalization circuit corresponding to the two channel rates.
In a prior art two types of clock reproduction circuits and reproduction equalization circuits are used by being switched in accordance with those two channel rates. An example of such a conventional magnetic tape reproduction unit is described in reference to the drawing in the following.
FIG. 9 shows a conventional multi-rate clock generator and multi-rate digital data reproducing device. In FIG. 9, a reproducer 1 reproduces the digitally recorded data at the first and the second channel rates.
The first rate reproduction equalizer 70 corrects the frequency characteristics of the reproduction signals reproduced at the first channel rate into desired frequency characteristics. The first rate signal discriminator 71 discriminates the output of the first rate reproduction equalizer 70 at the first sample rate so as to be decoded into the original digital data. The first rate voltage control oscillator 74 generates the clock of the basic frequency at the first channel rate, of which the frequency is variable due to the voltage. The first rate phase error detector 72 detects the phase shift between the clock generated by the first rate voltage control oscillator 74 and the reproduction signal reproduced at the first channel rate. The first rate loop filter 73 removes the high frequency component of the output of the first rate phase error detector 72 so as to control the oscillation frequency of the first rate voltage control oscillator 74 with that output.
The second rate reproduction equalizer 75 corrects the frequency characteristics of the reproduction signals reproduced at the second channel rate into the desired frequency characteristics. The second rate signal discriminator 76 discriminates the output of the second rate reproduction equalizer 75 at the second sample rate so as to be decoded into the original digital data. The second rate voltage control oscillator 79 generates the clock of the basic frequency at the second channel rate, of which the frequency is variable due to the voltage. The second rate phase error detector 77 detects a phase shift between the clock generated by the second rate voltage control oscillator 79 and the reproduction signal reproduced at the second channel rate. The second rate loop filter 78 removes the high frequency component of the output of the second rate phase error detector 77 so as to control the oscillation frequency of the second rate voltage control oscillator 79 with that output.
A reproduction data switch 80 outputs an input signal from the first rate signal discriminator 71 when reproducing at the first channel rate and outputs an input signal from the second rate signal discriminator 76 when reproducing at the second channel rate. A reproduction clock switch 81 outputs an input signal from the first rate voltage control oscillator 74 when reproducing at the first channel rate and outputs an input signal from the second rate voltage control oscillator 79 when reproducing at the second channel rate.
The conventional magnetic tape reproduction unit constructed as above generates the clock in accordance with the reproduction signal of the first channel rate by a PLL (Phase Locked Loop) circuit comprising the first rate phase error detector 72, the first rate loop filter 73 and the first rate voltage control oscillator 74 when the reproducer 1 reproduces data at the first channel rate and decodes the recorded original digital data after the first rate reproduction equalizer 70 and the first rate signal discriminator 71 correct the frequency characteristics of the reproduction signal.
In the same way, when the reproducer 1 reproduces the data at the second channel rate the clock is generated in accordance with the reproduction signal of the second channel rate by a PLL (Phase Locked Loop) circuit comprising the second rate phase error detector 77, the second rate loop filter 78 and the second rate voltage control oscillator 79 and the original digital data are decoded at the second channel rate after the second rate reproduction equalizer 75 and the second rate signal discriminator 76 correct the frequency characteristics of the reproduction signal.
In the above described construction, however, a plurality of voltage control oscillators, phase error detectors, loop filters and reproduction equalizers become necessary in accordance with the plurality of reproduced channel rates.
A purpose of the present invention is to provide a multi-rate clock generator which makes it possible to generate clocks in accordance with a plurality of reproduction channel rates by a phase error detector, a voltage control oscillator and a loop filter, of which the loop delay and the loop sensitivity are constant irrespective of the rate.
Another purpose of the present invention is to provide a multi-rate digital data reproducing device which makes it possible to decode the reproduction signal into the recorded original digital data in accordance with a plurality of reproduction channel rates by a reproduction equalizer, a phase error detector, a voltage control oscillator and a loop filter.
A multi-rate clock generator according to the first aspect of the invention is a multi-rate clock generator for generating clocks in accordance with a plurality of reproduced channel data rates, comprising: a reproduction means for reproducing the recorded digital data at a plurality of channel data rates which are n/m (n and m are positive integers) of a predetermined basic channel rate; a clock generation means for generating the first clock corresponding to the basic frequency of the basic channel rate of which the oscillation frequency is variable; an n/m division means for the n/m division of the first clock in accordance with the channel data rate of the reproduction means so as to output the second clock; an A/D conversion means for converting an input signal inputted from the reproduction means to a digital signal with the second clock; a phase error detection means for detecting a phase shift between an output of the A/D conversion means and the second clock based on the output of the A/D conversion means so as to output a phase error signal; and a digital filter means for processing the phase error signal with the second clock, wherein the clock generation means, the division means, the phase error detection means and the digital filter means form a PLL means by controlling the oscillation frequency of the clock generation means with the output signal of the digital filter means.
According to this multi-rate clock generator, in the multi-rate clock generator for generating a reproduction clock synchronized to a reproduction signal from the reproduction signal gained by reproducing the recorded digital data at a plurality of channel data rates which is n/m (n and m are positive integers) of the basic channel rate, the second clock (reproduction clock) is gained by n/m division of the first clock which is an output of a single clock generation means which oscillates at the basic frequency of said basic channel rate. Then using the second clock the reproduction signal is A/D converted and a phase shift between the A/D converted digital data and the above described second clock is detected to find a phase error signal and the low frequency component of the phase error signal is taken out by the digital filter means so as to generate a control signal of the above described clock generation means, which generates the second clock synchronized with the reproduction data.
A loop filter used in such a PLL means is constructed with a digital filter means which uses, as its process clock, the second clock (reproduction clock) which is gained by the n/m division of the first clock which is an output of the clock generation means and, thereby, the frequency characteristics of the digital filter means vary with a division ratio of n/m in a similar manner. Therefore, a multi-rate clock generator where the loop delay and the loop sensitivity of the PLL means are always constant, even when the channel rate varies, can be implemented with only one clock generation means, one division means, one phase error detection means and one digital filter means.
That is to say, in this multi-rate clock generator, the frequency characteristics of the digital filter means vary in a similar manner by changing the division ratio of the n/m division means (from n/m=1 to n/m=1/2) even when the reproduced channel data rate varies (for example, from n/m=1 to n/m=1/2). Thereby, the PLL means comprising a clock generation means, division means, phase error detection means and a digital filter means can be implemented with a single circuit construction even in the case that the reproduction channel rate varies, and a multi-rate clock generator can be gained where the loop sensitivity and the loop delay are constant for all of the channel rates.
A multi-rate digital data reproducing device according to the second aspect of the invention is a multi-rate digital data reproducing device for reproducing recorded digital data in accordance with a plurality of reproduced channel data rates, comprising: a reproduction means for reproducing recorded digital data at a plurality of channel data rates which are n/m (n and m are positive integers) of a predetermined basic channel rate; a clock generation means for generating the first clock corresponding to the basic frequency of the basic channel rate of which the oscillation frequency is variable; an n/m division for the n/m division of the first clock in accordance with the channel data rate of the reproduction means so as to output the second clock; an A/D conversion means for converting an input signal inputted from the reproduction means to a digital signal with the second clock; a phase error detection means for detecting a phase shift between the output of the A/D conversion means and the second clock based on the output of the A/D conversion means so as to output a phase error signal; the first digital filter means for processing the phase error signal with the second clock; a reproduction equalization means comprising the second digital filter means for processing the output of the A/D conversion means with the second clock; and a discrimination means for reproducing the recorded original digital data from the output signal of the second digital filter means, wherein the multi-rate digital data reproducing device is characterized in that the clock generation means, the division means, the phase error detection means and the first digital filter means form a PLL means by controlling the oscillation frequency of the clock generation means with the output signal of the first digital filter means and that the originally recorded data are reproduced in accordance with a plurality of channel data rates which are reproduced by said second digital filter means.
According to this multi-rate digital data reproducing device, in the device which decodes a reproduction signal varying at the plurality of channel data rates which are n/m of the basic channel rate into the original recorded digital data, the filter means used in the reproduction equalization means which corrects to the frequency characteristics needed for the decoding is constructed with the second digital filter means, of which the process clock the second clock used as the reproduction clock divided to n/m. Thereby, since the frequency characteristics of the above described reproduction equalizer vary with the n/m division ratio in a similar manner, respective constants for determining the filter characteristics need not be reset or readjusted even when the reproduction channel rate varies so as to automatically have the characteristics suitable for each channel rate. Thereby, a multi-rate digital data reproducing device can be implemented with only one reproduction equalization means.
That is to say, in this multi-rate digital data reproducing device, the frequency characteristics of the first digital filter and the second digital filter vary in a similar manner by changing the division ratio of the n/m division means (from n/m=1 to n/m=1/2) even when the reproduced channel data rate varies (for example, from n/m=1 to n/m=1/2). Thereby, the PLL means comprising a clock generation means, a division means, a phase error detection means and the first digital filter means as well as the reproduction equalization means comprising the second digital filter means can be implemented with a single circuit construction even in the case that the reproduction channel rate varies, and a multi-rate digital data reproducing device can be gained of which the loop sensitivity and the loop delay are constant for all of the channel rates. The other points are the same as in the multi-rate clock generator according to the first aspect of the invention.
A multi-rate digital data reproducing device according to the third aspect of the invention is a multi-rate digital data reproducing device which corrects a reproduction signal, of which the amplitude fluctuates, to a desired amplitude level, even when the channel data rate of the reproduction signal varies, comprising: a reproduction means for reproducing recorded digital data at a plurality of channel data rates which are n/m (n and m are positive integers) of a predetermined basic channel rate; a clock generation means for generating the first clock corresponding to the basic frequency of the basic channel rate of which the oscillation frequency is variable; an n/m division means for the n/m division of the first clock in accordance with the channel data rate of the reproduction means so as to output the second clock, an A/D conversion means for gaining the first reproduction signal by converting an input signal inputted from the reproduction means to a digital signal with the second clock; a phase error detection means for detecting a phase shift between the output of the A/D conversion means and the second clock so as to output a phase error signal; the first digital filter means for processing the phase error signal with the second clock; a multiplication means for gaining the second reproduction signal by multiplying the first reproduction signal outputted by the A/D conversion means by the first control signal; an amplitude error detection means for detecting a difference between the second reproduction signal and a predetermined target level; and the second digital filter means for processing the output of the amplitude error detection means with the second clock so as to output the first control signal, wherein the clock generation means, the division means, the phase error detection means and the first digital filter means form a PLL means by controlling the oscillation frequency of the clock generation means with the output signal of the first digital filter means.
According to this multi-rate digital data reproducing device, it is understood that the frequency characteristics of the first digital filter vary in a similar manner by changing the division ratio of the n/m division means (first rate n/m=1 to n/m=1/2) even when the reproduced channel data rate varies (for example, from n/m=1 to n/m=1/2). Thereby, the PLL means comprising the phase error detection means, the loop filter, the oscillation frequency controller and a clock generation means can be realized with a single circuit construction even in the case the reproduction channel rate varies, and a multi-rate digital data reproducing device can be gained of which the loop sensitivity and the loop delay are constant for all of the channel rates.
In addition, according to this multi-rate digital data reproducing device, even when a reproduction channel rate of the reproduction signal, of which the amplitude fluctuates with the oscillation frequency having a predetermined ratio to the reproduction channel rate, varies the frequency characteristics of the filter means vary in a similar manner with the division ratio of n/m by using the second clock as the reproduction clock, which is divided to n/m for its process clock, wherein the filter means for detecting the above described amplitude fluctuation frequency is constructed with the second digital filter means. Therefore, even when the reproduction channel rate varies, it is not necessary to reset or readjust respective constants for determining the filter characteristics, which makes it possible to automatically detect the amplitude fluctuation frequency suitable for each channel rate. Thereby, a multi-rate digital data reproducing device with an amplitude fluctuation correction function can be implemented with only one filter means. The other effects are the same in the multi-rate clock generator according to the first aspect of the invention.
A multi-rate digital data reproducing device according to the fourth aspect of the invention is a multi-rate digital data reproducing device for detecting, from a reproduction signal of which the standard signal is multiplied to a predetermined frequency which is, when a channel data rate varies, 1/d of the channel data rate, the standard signal so as to detect the condition of the reproduced signal, comprising: a reproduction means for reproducing recorded digital data with a plurality of channel data rates which are n/m (n and m are positive integers) of a predetermined basic channel rate; a clock generation means for generating the first clock corresponding to the basic frequency of the basic channel rate of which the oscillation frequency is variable; an n/m division means for the n/m division of the first clock in accordance with the channel data rate of the reproduction means so as to output the second clock; an A/D conversion means for converting an input signal inputted from the reproduction means to a digital signal with the second clock so as to gain the first reproduction signal; a phase error detection means for detecting a phase shift between the output of the A/D conversion means and the second clock based on the output of the A/D conversion means so as to output a phase error signal; the first digital filter means for processing the phase error signal with the second clock, the second digital filter means for processing the first reproduction signal outputted by the A/D conversion means with the second clock so as to pass a predetermined frequency which is 1/d of the channel data rate; and a reproduction condition detection means for detecting the reproduction condition of the first reproduction signal by detecting the signal level which passes through the second digital filter means, wherein the clock generation means, the division means, the phase error detection means and the first digital filter means form a PLL means by controlling the oscillation frequency of the clock generation means with the output signal of the first digital filter means.
According to this multi-rate digital data reproducing device the frequency characteristics of the first digital filter vary in a similar manner by varying the division ratio of the n/m division means (first rate n/m=1 to n/m=1/2) even when the reproduced channel data rate varies (for example, first rate n/m=1 to n/m=1/2). Thereby, the PLL means comprising a phase error detection means, a loop filter, an oscillation frequency controller and a clock generation means can be implemented with a single circuit construction even in the case that the reproducing channel rate varies, and a multi-rate digital data reproducing device can be gained of which the loop sensitivity and the loop delay are constant for all the channel rates.
In addition, according to this multi-rate digital data reproducing device, even when the reproduction channel rate of the reproduction signal, with which a pilot signal with the frequency having a predetermined ratio to the reproduction channel rate is multiplied in frequency, varies the frequency characteristics of the filter means varies in a similar manner with a division ratio of n/m by constructing the filter means for detecting the above described pilot signal with the second digital filter means and by using the second clock as the reproduction clock gained by the n/m division of the process clock. Therefore, even when the reproduction channel rate varies, it is not necessary to reset or to readjust respective constants for determining filter characteristics, which makes it possible to automatically detect the pilot signal suitable for respective channel rates. Thereby, a multi-rate digital data reproducing device with a power signal detection function can be implemented with only one filter means. The other points are the same as in the multi-rate clock generator according to the first aspect of the invention.